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//new print implementationendfunctionendclassThere will be no difference.Using virtual keyword to override a default function is not necessary in derived class, but neither there is an error.//overriding definitionsuper .// Base handle points to ext objpkt .This is because when virtual methods are used, SystemVerilog uses the type of the object and not the handle to decide which routine to call.}SystemVerilog data types are the only data types that can cross the boundary between SystemVerilog and a foreign language in either direction.Both functions and tasks can be either imported or exported.What are system tasks and functions?Give some example of system tasks and functions with their purpose.In addition, language also supports addition of user defined system tasks and functions.Candidate is then asked to define a verification strategy and explain the steps to verify that design.In this way, an interviewer can test a candidate for his/her general awareness and experience on verification as well as judge how well a candidate can think, analyze and solve given a problem statement.Following section contains questions that are designed to help you crack this segment of an interview.Additionally, this section also contains some commonly asked questions related to fundamentals of Verification.A Recent College Graduate may not be asked a lot of questions from this section, whereas this section may constitute a considerable portion of interview for a Senior candidate.In an interview, difficulty of this section varies with the experience of the candidate.What are the advantages and disadvantage of both?Directed testing is an approach where a directed test is written for verifying each of the features in the design.On the other hand, constrained random testing is an approach in which a stimulus is generated automatically using constrained random generators that generates stimulus as per design specification.What is Coverage driven verification?In Coverage driven Verification methodology , a verification plan is implemented by mapping each of the feature or scenario into a coverage monitor that can be used to collect coverage information during simulation.Sometimes, a corner case in the design may not be covered easily using constrained random stimulus and might be better done using a directed test.